A clock generator is essential in modern computer systems and consumer products. A clock generator with a delay-locked loop (DLL) may be employed in a computer system as a clock generator or radio communication as a clock synthesizer. Most clock generators adopt phase-locked loop (PLL) scheme; however, a delay-locked loop (DLL) having features of low jitter, better stability and small area is more suitable than a phase-locked loop as a clock multiplier.
A traditional DLL-based clock generator 100 is illustrates in FIG. 1. A reference frequency Fin is delivered into the voltage control delay line 101 and the phase detector 102. The phase detector 102 detects the phase of the input frequency Fin and generates control signals to the charge pump 103 for charge and discharge operation. The low pass filter 104 filters the output signals of the charge pump 103. The voltage controlled delay line 101 generates multi-phase signals to the edge combiner 105 in response to the reference frequency Fin and the filleted signal from the low pass filter 104. The edge combiner 105 is used as a local oscillator in the clock generator 100 to generator an output frequency Fout multiplied by a ratio of the input frequency. The programmable scheme was not realized.
A differential symmetric load delay element and current starved delay element used in the voltage control delay line 101 is illustrated in FIG. 2 and FIG. 3.
The delay element in FIG. 2 includes a plurality of transistors forming a differential pair. PMOS 111 and 112 are connected in parallel, while PMOS 113 and 114, which form a symmetry load, are connected in parallel. The input signals Vi+, Vi− are delivered to the gate of the NOMS 115, 116 and the output signals Vo+, Vo− are obtained at the source of the NMOS 115 and the NMOS 116 respectively.
The delay element in FIG. 3 includes a plurality of transistors. The transistors 121, 122 are PMOS. The input signal Vi is delivered to the gate of the PMOS 123 and NMOS 124, while the output signal Vo is obtained at the drain of the PMOS 125 and the source of the NMOS 126. Further, NMOS 127 is connected with the PMOS 121, and NMOS 128 is connected with the NMOS 124.
The circuit in FIG. 2 may have drawback of unbalanced rise and fall operation. Therefore, the duty cycle is dependent on the control voltage. Further, there is a dependency on the output signal jitter according to the unbalanced operation. The circuit also consumes DC power with no full swing output signal. The variable amplitude of the output signal leads to asymmetrical charging and discharging operation. Thus, a non-50% duty cycle occurs owing to the rise and fall delay. The traditional current starved delay elements perform nonlinear delay characteristic. The circuits in FIGS. 2 and 3 have a very nonlinear delay feature. The delay time versus the controlling voltage curve performs high gain including signal jitter, When the control voltage is smaller than the threshold voltage (Vgs<Vtn) of the system, the conducting current would be very small and the delay time increases to a very large scale.
The edge combiner used in the clock generator of the prior art is illustrated in FIG. 4. It has a limitation on the minimum supply voltage because of its source-follower structure N1, N2 and three inverters 131˜133 are connected in series, the output terminal of the last of which is connected to the gate of the NMOS N1. The drain of N1 is connected to the gate of the PMOS P1 and the drain of the PMOS P3 respectively, while the source of N2 is connected to the PMOS P2 and the drain of the NMOS N3.
If the signal at the node Q is VDD, then the signal at the node X is VDD, At the rising edges of the signals A1, A2, . . . An, the signal at the node Y is pulled up through the source follower structure composed of two NMOSs N1 and N2. If the signal at the node Q is GND, then the signal at node Y is GND. At the rising edges of the signals A1, A2, . . . An, the signal at the node X is pulled downed through N1 and N2. The weak cross-coupled inverters are used to obtain full-swing signals and avoid floating of the signals at the nodes X and Y. The discharge of the signal at node X and charge of the signal at node Y are asymmetrical. It is difficult to obtain equal rise and fall operation of the signal at the node Q. The asymmetrical rise and fall delay results in a larger jitter on the output signal, Moreover, the source follower structure has limitation on the minimum supply voltage and maximum operating frequency. The structure also has a drawback of asymmetric rise and fall performance.
A DLL-based frequency synthesizer used AND-OR gates as a combiner to multiply the input frequency by fixed times. The programmable scheme is not realized. Moreover, the signal delay paths through the multi-input logic gates are complicated. The rise and fall delay time are difficult to be balanced.